/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

/**
 * @file  dwc_ether_qos_wrapper_reg.h
 * @brief Semidrive. AUTOSAR 4.3.1 MCAL Eth plugins.
 */


/* Generated by tool. Do not modify manually. */

#ifndef DWC_ETHER_QOS_WRAPPER_REG_H
#define DWC_ETHER_QOS_WRAPPER_REG_H

#define APB_ERR_INT_SIG_EN_OFF  0x2008U

#define BM_APB_ERR_INT_SIG_EN_PRDATA_PARITY_ERR (0x01U << 5U)

#define BM_APB_ERR_INT_SIG_EN_PWDATA_FATAL  (0x01U << 4U)

#define BM_APB_ERR_INT_SIG_EN_PWDATA_UNCERR (0x01U << 3U)

#define BM_APB_ERR_INT_SIG_EN_PWDATA_CORERR (0x01U << 2U)

#define BM_APB_ERR_INT_SIG_EN_PCTL_UNCERR   (0x01U << 1U)

#define BM_APB_ERR_INT_SIG_EN_PADDR_UNCERR  (0x01U << 0U)

#define REG_PARITY_ERR_INT_STAT_OFF 0x2010U

#define BM_REG_PARITY_ERR_INT_STAT_REG_PARITY_ERR   (0x01U << 0U)

#define REG_PARITY_ERR_INT_STAT_EN_OFF  0x2014U

#define BM_REG_PARITY_ERR_INT_STAT_EN_REG_PARITY_ERR    (0x01U << 0U)

#define REG_PARITY_ERR_INT_SIG_EN_OFF   0x2018U

#define BM_REG_PARITY_ERR_INT_SIG_EN_REG_PARITY_ERR (0x01U << 0U)

#define PRDATAINJ_OFF   0x201cU

#define BM_PRDATAINJ_ERR_INJ    (0x01U << 0U)

#define INPUT_ERR_INT_STA_OFF   0x2020U

#define BM_INPUT_ERR_INT_STA_REG_PARITY_EJ_EN   (0x01U << 1U)

#define BM_INPUT_ERR_INT_STA_SELFTEST_MODE  (0x01U << 0U)

#define INPUT_ERR_INT_STA_EN_OFF    0x2024U

#define BM_INPUT_ERR_INT_STA_EN_REG_PARITY_EJ_EN    (0x01U << 1U)

#define BM_INPUT_ERR_INT_STA_EN_SELFTEST_MODE   (0x01U << 0U)

#define INPUT_ERR_INT_SIG_EN_OFF    0x2028U

#define BM_INPUT_ERR_INT_SIG_EN_REG_PARITY_EJ_EN    (0x01U << 1U)

#define BM_INPUT_ERR_INT_SIG_EN_SELFTEST_MODE   (0x01U << 0U)

#define DMA_ERR_INT_STA_OFF 0x2030U

#define BM_DMA_ERR_INT_STA_DMA3_MULTI_REQ_ERR   (0x01U << 29U)

#define BM_DMA_ERR_INT_STA_DMA3_EOBC_ERR    (0x01U << 28U)

#define BM_DMA_ERR_INT_STA_DMA3_EOBA_ERR    (0x01U << 27U)

#define BM_DMA_ERR_INT_STA_DMA3_BW_FATAL_ERR    (0x01U << 26U)

#define BM_DMA_ERR_INT_STA_DMA3_BW_UNC_ERR  (0x01U << 25U)

#define BM_DMA_ERR_INT_STA_DMA3_BW_COR_ERR  (0x01U << 24U)

#define BM_DMA_ERR_INT_STA_DMA2_MULTI_REQ_ERR   (0x01U << 21U)

#define BM_DMA_ERR_INT_STA_DMA2_EOBC_ERR    (0x01U << 20U)

#define BM_DMA_ERR_INT_STA_DMA2_EOBA_ERR    (0x01U << 19U)

#define BM_DMA_ERR_INT_STA_DMA2_BW_FATAL_ERR    (0x01U << 18U)

#define BM_DMA_ERR_INT_STA_DMA2_BW_UNC_ERR  (0x01U << 17U)

#define BM_DMA_ERR_INT_STA_DMA2_BW_COR_ERR  (0x01U << 16U)

#define BM_DMA_ERR_INT_STA_DMA1_MULTI_REQ_ERR   (0x01U << 13U)

#define BM_DMA_ERR_INT_STA_DMA1_EOBC_ERR    (0x01U << 12U)

#define BM_DMA_ERR_INT_STA_DMA1_EOBA_ERR    (0x01U << 11U)

#define BM_DMA_ERR_INT_STA_DMA1_BW_FATAL_ERR    (0x01U << 10U)

#define BM_DMA_ERR_INT_STA_DMA1_BW_UNC_ERR  (0x01U << 9U)

#define BM_DMA_ERR_INT_STA_DMA1_BW_COR_ERR  (0x01U << 8U)

#define BM_DMA_ERR_INT_STA_DMA0_MULTI_REQ_ERR   (0x01U << 5U)

#define BM_DMA_ERR_INT_STA_DMA0_EOBC_ERR    (0x01U << 4U)

#define BM_DMA_ERR_INT_STA_DMA0_EOBA_ERR    (0x01U << 3U)

#define BM_DMA_ERR_INT_STA_DMA0_BW_FATAL_ERR    (0x01U << 2U)

#define BM_DMA_ERR_INT_STA_DMA0_BW_UNC_ERR  (0x01U << 1U)

#define BM_DMA_ERR_INT_STA_DMA0_BW_COR_ERR  (0x01U << 0U)

#define DMA_ERR_INT_STA_EN_OFF  0x2034U

#define BM_DMA_ERR_INT_STA_EN_DMA3_MULTI_REQ_ERR    (0x01U << 29U)

#define BM_DMA_ERR_INT_STA_EN_DMA3_EOBC_ERR (0x01U << 28U)

#define BM_DMA_ERR_INT_STA_EN_DMA3_EOBA_ERR (0x01U << 27U)

#define BM_DMA_ERR_INT_STA_EN_DMA3_BW_FATAL_ERR (0x01U << 26U)

#define BM_DMA_ERR_INT_STA_EN_DMA3_BW_UNC_ERR   (0x01U << 25U)

#define BM_DMA_ERR_INT_STA_EN_DMA3_BW_COR_ERR   (0x01U << 24U)

#define BM_DMA_ERR_INT_STA_EN_DMA2_MULTI_REQ_ERR    (0x01U << 21U)

#define BM_DMA_ERR_INT_STA_EN_DMA2_EOBC_ERR (0x01U << 20U)

#define BM_DMA_ERR_INT_STA_EN_DMA2_EOBA_ERR (0x01U << 19U)

#define BM_DMA_ERR_INT_STA_EN_DMA2_BW_FATAL_ERR (0x01U << 18U)

#define BM_DMA_ERR_INT_STA_EN_DMA2_BW_UNC_ERR   (0x01U << 17U)

#define BM_DMA_ERR_INT_STA_EN_DMA2_BW_COR_ERR   (0x01U << 16U)

#define BM_DMA_ERR_INT_STA_EN_DMA1_MULTI_REQ_ERR    (0x01U << 13U)

#define BM_DMA_ERR_INT_STA_EN_DMA1_EOBC_ERR (0x01U << 12U)

#define BM_DMA_ERR_INT_STA_EN_DMA1_EOBA_ERR (0x01U << 11U)

#define BM_DMA_ERR_INT_STA_EN_DMA1_BW_FATAL_ERR (0x01U << 10U)

#define BM_DMA_ERR_INT_STA_EN_DMA1_BW_UNC_ERR   (0x01U << 9U)

#define BM_DMA_ERR_INT_STA_EN_DMA1_BW_COR_ERR   (0x01U << 8U)

#define BM_DMA_ERR_INT_STA_EN_DMA0_MULTI_REQ_ERR    (0x01U << 5U)

#define BM_DMA_ERR_INT_STA_EN_DMA0_EOBC_ERR (0x01U << 4U)

#define BM_DMA_ERR_INT_STA_EN_DMA0_EOBA_ERR (0x01U << 3U)

#define BM_DMA_ERR_INT_STA_EN_DMA0_BW_FATAL_ERR (0x01U << 2U)

#define BM_DMA_ERR_INT_STA_EN_DMA0_BW_UNC_ERR   (0x01U << 1U)

#define BM_DMA_ERR_INT_STA_EN_DMA0_BW_COR_ERR   (0x01U << 0U)

#define DMA_ERR_INT_SIG_EN_OFF  0x2038U

#define BM_DMA_ERR_INT_SIG_EN_DMA3_MULTI_REQ_ERR    (0x01U << 29U)

#define BM_DMA_ERR_INT_SIG_EN_DMA3_EOBC_ERR (0x01U << 28U)

#define BM_DMA_ERR_INT_SIG_EN_DMA3_EOBA_ERR (0x01U << 27U)

#define BM_DMA_ERR_INT_SIG_EN_DMA3_BW_FATAL_ERR (0x01U << 26U)

#define BM_DMA_ERR_INT_SIG_EN_DMA3_BW_UNC_ERR   (0x01U << 25U)

#define BM_DMA_ERR_INT_SIG_EN_DMA3_BW_COR_ERR   (0x01U << 24U)

#define BM_DMA_ERR_INT_SIG_EN_DMA2_MULTI_REQ_ERR    (0x01U << 21U)

#define BM_DMA_ERR_INT_SIG_EN_DMA2_EOBC_ERR (0x01U << 20U)

#define BM_DMA_ERR_INT_SIG_EN_DMA2_EOBA_ERR (0x01U << 19U)

#define BM_DMA_ERR_INT_SIG_EN_DMA2_BW_FATAL_ERR (0x01U << 18U)

#define BM_DMA_ERR_INT_SIG_EN_DMA2_BW_UNC_ERR   (0x01U << 17U)

#define BM_DMA_ERR_INT_SIG_EN_DMA2_BW_COR_ERR   (0x01U << 16U)

#define BM_DMA_ERR_INT_SIG_EN_DMA1_MULTI_REQ_ERR    (0x01U << 13U)

#define BM_DMA_ERR_INT_SIG_EN_DMA1_EOBC_ERR (0x01U << 12U)

#define BM_DMA_ERR_INT_SIG_EN_DMA1_EOBA_ERR (0x01U << 11U)

#define BM_DMA_ERR_INT_SIG_EN_DMA1_BW_FATAL_ERR (0x01U << 10U)

#define BM_DMA_ERR_INT_SIG_EN_DMA1_BW_UNC_ERR   (0x01U << 9U)

#define BM_DMA_ERR_INT_SIG_EN_DMA1_BW_COR_ERR   (0x01U << 8U)

#define BM_DMA_ERR_INT_SIG_EN_DMA0_MULTI_REQ_ERR    (0x01U << 5U)

#define BM_DMA_ERR_INT_SIG_EN_DMA0_EOBC_ERR (0x01U << 4U)

#define BM_DMA_ERR_INT_SIG_EN_DMA0_EOBA_ERR (0x01U << 3U)

#define BM_DMA_ERR_INT_SIG_EN_DMA0_BW_FATAL_ERR (0x01U << 2U)

#define BM_DMA_ERR_INT_SIG_EN_DMA0_BW_UNC_ERR   (0x01U << 1U)

#define BM_DMA_ERR_INT_SIG_EN_DMA0_BW_COR_ERR   (0x01U << 0U)

#define PWDATA_INJ_OFF  0x2040U

#define FM_PWDATA_INJ_DATA_INJ  (0xffffffffU << 0U)
#define FV_PWDATA_INJ_DATA_INJ(v) \
    (((v) << 0U) & FM_PWDATA_INJ_DATA_INJ)
#define GFV_PWDATA_INJ_DATA_INJ(v) \
    (((v) & FM_PWDATA_INJ_DATA_INJ) >> 0U)

#define PWECC_INJ_OFF   0x2044U

#define FM_PWECC_INJ_ECC_INJ    (0x7fU << 0U)
#define FV_PWECC_INJ_ECC_INJ(v) \
    (((v) << 0U) & FM_PWECC_INJ_ECC_INJ)
#define GFV_PWECC_INJ_ECC_INJ(v) \
    (((v) & FM_PWECC_INJ_ECC_INJ) >> 0U)

#define INT_ERR_INJ_OFF 0x2048U

#define BM_INT_ERR_INJ_PMT_INTR (0x01U << 16U)

#define FM_INT_ERR_INJ_SBD_PERCH_RX_INTR    (0x1fU << 11U)
#define FV_INT_ERR_INJ_SBD_PERCH_RX_INTR(v) \
    (((v) << 11U) & FM_INT_ERR_INJ_SBD_PERCH_RX_INTR)
#define GFV_INT_ERR_INJ_SBD_PERCH_RX_INTR(v) \
    (((v) & FM_INT_ERR_INJ_SBD_PERCH_RX_INTR) >> 11U)

#define FM_INT_ERR_INJ_SBD_PERCH_TX_INTR    (0x1fU << 6U)
#define FV_INT_ERR_INJ_SBD_PERCH_TX_INTR(v) \
    (((v) << 6U) & FM_INT_ERR_INJ_SBD_PERCH_TX_INTR)
#define GFV_INT_ERR_INJ_SBD_PERCH_TX_INTR(v) \
    (((v) & FM_INT_ERR_INJ_SBD_PERCH_TX_INTR) >> 6U)

#define BM_INT_ERR_INJ_SBD_SFTY_UE_INTR (0x01U << 5U)

#define BM_INT_ERR_INJ_SBD_SFTY_CE_INTR (0x01U << 4U)

#define BM_INT_ERR_INJ_SBD_INTR (0x01U << 3U)

#define BM_INT_ERR_INJ_LPI_INTR (0x01U << 2U)

#define BM_INT_ERR_INJ_UNC_ERR  (0x01U << 1U)

#define BM_INT_ERR_INJ_COR_ERR  (0x01U << 0U)

#define DMA0_ERR_INJ_OFF    0x2050U

#define FM_DMA0_ERR_INJ_BW_CODE_INJ (0xfU << 12U)
#define FV_DMA0_ERR_INJ_BW_CODE_INJ(v) \
    (((v) << 12U) & FM_DMA0_ERR_INJ_BW_CODE_INJ)
#define GFV_DMA0_ERR_INJ_BW_CODE_INJ(v) \
    (((v) & FM_DMA0_ERR_INJ_BW_CODE_INJ) >> 12U)

#define FM_DMA0_ERR_INJ_BW_DATA_INJ (0xfU << 8U)
#define FV_DMA0_ERR_INJ_BW_DATA_INJ(v) \
    (((v) << 8U) & FM_DMA0_ERR_INJ_BW_DATA_INJ)
#define GFV_DMA0_ERR_INJ_BW_DATA_INJ(v) \
    (((v) & FM_DMA0_ERR_INJ_BW_DATA_INJ) >> 8U)

#define FM_DMA0_ERR_INJ_FW_CODE_INJ (0xfU << 4U)
#define FV_DMA0_ERR_INJ_FW_CODE_INJ(v) \
    (((v) << 4U) & FM_DMA0_ERR_INJ_FW_CODE_INJ)
#define GFV_DMA0_ERR_INJ_FW_CODE_INJ(v) \
    (((v) & FM_DMA0_ERR_INJ_FW_CODE_INJ) >> 4U)

#define FM_DMA0_ERR_INJ_FW_DATA_INJ (0x7U << 0U)
#define FV_DMA0_ERR_INJ_FW_DATA_INJ(v) \
    (((v) << 0U) & FM_DMA0_ERR_INJ_FW_DATA_INJ)
#define GFV_DMA0_ERR_INJ_FW_DATA_INJ(v) \
    (((v) & FM_DMA0_ERR_INJ_FW_DATA_INJ) >> 0U)

#define DMA1_ERR_INJ_OFF    0x2054U

#define FM_DMA1_ERR_INJ_BW_CODE_INJ (0xfU << 12U)
#define FV_DMA1_ERR_INJ_BW_CODE_INJ(v) \
    (((v) << 12U) & FM_DMA1_ERR_INJ_BW_CODE_INJ)
#define GFV_DMA1_ERR_INJ_BW_CODE_INJ(v) \
    (((v) & FM_DMA1_ERR_INJ_BW_CODE_INJ) >> 12U)

#define FM_DMA1_ERR_INJ_BW_DATA_INJ (0xfU << 8U)
#define FV_DMA1_ERR_INJ_BW_DATA_INJ(v) \
    (((v) << 8U) & FM_DMA1_ERR_INJ_BW_DATA_INJ)
#define GFV_DMA1_ERR_INJ_BW_DATA_INJ(v) \
    (((v) & FM_DMA1_ERR_INJ_BW_DATA_INJ) >> 8U)

#define FM_DMA1_ERR_INJ_FW_CODE_INJ (0xfU << 4U)
#define FV_DMA1_ERR_INJ_FW_CODE_INJ(v) \
    (((v) << 4U) & FM_DMA1_ERR_INJ_FW_CODE_INJ)
#define GFV_DMA1_ERR_INJ_FW_CODE_INJ(v) \
    (((v) & FM_DMA1_ERR_INJ_FW_CODE_INJ) >> 4U)

#define FM_DMA1_ERR_INJ_FW_DATA_INJ (0x7U << 0U)
#define FV_DMA1_ERR_INJ_FW_DATA_INJ(v) \
    (((v) << 0U) & FM_DMA1_ERR_INJ_FW_DATA_INJ)
#define GFV_DMA1_ERR_INJ_FW_DATA_INJ(v) \
    (((v) & FM_DMA1_ERR_INJ_FW_DATA_INJ) >> 0U)

#define DMA2_ERR_INJ_OFF    0x2058U

#define FM_DMA2_ERR_INJ_BW_CODE_INJ (0xfU << 12U)
#define FV_DMA2_ERR_INJ_BW_CODE_INJ(v) \
    (((v) << 12U) & FM_DMA2_ERR_INJ_BW_CODE_INJ)
#define GFV_DMA2_ERR_INJ_BW_CODE_INJ(v) \
    (((v) & FM_DMA2_ERR_INJ_BW_CODE_INJ) >> 12U)

#define FM_DMA2_ERR_INJ_BW_DATA_INJ (0xfU << 8U)
#define FV_DMA2_ERR_INJ_BW_DATA_INJ(v) \
    (((v) << 8U) & FM_DMA2_ERR_INJ_BW_DATA_INJ)
#define GFV_DMA2_ERR_INJ_BW_DATA_INJ(v) \
    (((v) & FM_DMA2_ERR_INJ_BW_DATA_INJ) >> 8U)

#define FM_DMA2_ERR_INJ_FW_CODE_INJ (0xfU << 4U)
#define FV_DMA2_ERR_INJ_FW_CODE_INJ(v) \
    (((v) << 4U) & FM_DMA2_ERR_INJ_FW_CODE_INJ)
#define GFV_DMA2_ERR_INJ_FW_CODE_INJ(v) \
    (((v) & FM_DMA2_ERR_INJ_FW_CODE_INJ) >> 4U)

#define FM_DMA2_ERR_INJ_FW_DATA_INJ (0x7U << 0U)
#define FV_DMA2_ERR_INJ_FW_DATA_INJ(v) \
    (((v) << 0U) & FM_DMA2_ERR_INJ_FW_DATA_INJ)
#define GFV_DMA2_ERR_INJ_FW_DATA_INJ(v) \
    (((v) & FM_DMA2_ERR_INJ_FW_DATA_INJ) >> 0U)

#define DMA3_ERR_INJ_OFF    0x205cU

#define FM_DMA3_ERR_INJ_BW_CODE_INJ (0xfU << 12U)
#define FV_DMA3_ERR_INJ_BW_CODE_INJ(v) \
    (((v) << 12U) & FM_DMA3_ERR_INJ_BW_CODE_INJ)
#define GFV_DMA3_ERR_INJ_BW_CODE_INJ(v) \
    (((v) & FM_DMA3_ERR_INJ_BW_CODE_INJ) >> 12U)

#define FM_DMA3_ERR_INJ_BW_DATA_INJ (0xfU << 8U)
#define FV_DMA3_ERR_INJ_BW_DATA_INJ(v) \
    (((v) << 8U) & FM_DMA3_ERR_INJ_BW_DATA_INJ)
#define GFV_DMA3_ERR_INJ_BW_DATA_INJ(v) \
    (((v) & FM_DMA3_ERR_INJ_BW_DATA_INJ) >> 8U)

#define FM_DMA3_ERR_INJ_FW_CODE_INJ (0xfU << 4U)
#define FV_DMA3_ERR_INJ_FW_CODE_INJ(v) \
    (((v) << 4U) & FM_DMA3_ERR_INJ_FW_CODE_INJ)
#define GFV_DMA3_ERR_INJ_FW_CODE_INJ(v) \
    (((v) & FM_DMA3_ERR_INJ_FW_CODE_INJ) >> 4U)

#define FM_DMA3_ERR_INJ_FW_DATA_INJ (0x7U << 0U)
#define FV_DMA3_ERR_INJ_FW_DATA_INJ(v) \
    (((v) << 0U) & FM_DMA3_ERR_INJ_FW_DATA_INJ)
#define GFV_DMA3_ERR_INJ_FW_DATA_INJ(v) \
    (((v) & FM_DMA3_ERR_INJ_FW_DATA_INJ) >> 0U)

#define SELFTEST_MODE_OFF   0x2060U

#define BM_SELFTEST_MODE_EN (0x01U << 0U)

#define PPS_STRETCH_CFG_OFF 0x2070U

#define FM_PPS_STRETCH_CFG_PPS3_STRETCH_WIDTH  ((uint32)0x3fU << 26U)
#define FV_PPS_STRETCH_CFG_PPS3_STRETCH_WIDTH(v) \
  (((uint32)(v) << 26U) & FM_PPS_STRETCH_CFG_PPS3_STRETCH_WIDTH)
#define GFV_PPS_STRETCH_CFG_PPS3_STRETCH_WIDTH(v) \
  (((uint32)(v) & FM_PPS_STRETCH_CFG_PPS3_STRETCH_WIDTH) >> 26U)

#define BM_PPS_STRETCH_CFG_PPS3_PULSE_SEL  ((uint32)0x01U << 25U)

#define BM_PPS_STRETCH_CFG_PPS3_EN  ((uint32)0x01U << 24U)

#define FM_PPS_STRETCH_CFG_PPS2_STRETCH_WIDTH  ((uint32)0x3fU << 18U)
#define FV_PPS_STRETCH_CFG_PPS2_STRETCH_WIDTH(v) \
  (((uint32)(v) << 18U) & FM_PPS_STRETCH_CFG_PPS2_STRETCH_WIDTH)
#define GFV_PPS_STRETCH_CFG_PPS2_STRETCH_WIDTH(v) \
  (((uint32)(v) & FM_PPS_STRETCH_CFG_PPS2_STRETCH_WIDTH) >> 18U)

#define BM_PPS_STRETCH_CFG_PPS2_PULSE_SEL  ((uint32)0x01U << 17U)

#define BM_PPS_STRETCH_CFG_PPS2_EN  ((uint32)0x01U << 16U)

#define FM_PPS_STRETCH_CFG_PPS1_STRETCH_WIDTH  ((uint32)0x3fU << 10U)
#define FV_PPS_STRETCH_CFG_PPS1_STRETCH_WIDTH(v) \
  (((uint32)(v) << 10U) & FM_PPS_STRETCH_CFG_PPS1_STRETCH_WIDTH)
#define GFV_PPS_STRETCH_CFG_PPS1_STRETCH_WIDTH(v) \
  (((uint32)(v) & FM_PPS_STRETCH_CFG_PPS1_STRETCH_WIDTH) >> 10U)

#define BM_PPS_STRETCH_CFG_PPS1_PULSE_SEL  ((uint32)0x01U << 9U)

#define BM_PPS_STRETCH_CFG_PPS1_EN  ((uint32)0x01U << 8U)

#define FM_PPS_STRETCH_CFG_PPS0_STRETCH_WIDTH  ((uint32)0x3fU << 2U)
#define FV_PPS_STRETCH_CFG_PPS0_STRETCH_WIDTH(v) \
  (((uint32)(v) << 2U) & FM_PPS_STRETCH_CFG_PPS0_STRETCH_WIDTH)
#define GFV_PPS_STRETCH_CFG_PPS0_STRETCH_WIDTH(v) \
  (((uint32)(v) & FM_PPS_STRETCH_CFG_PPS0_STRETCH_WIDTH) >> 2U)

#define BM_PPS_STRETCH_CFG_PPS0_PULSE_SEL  ((uint32)0x01U << 1U)

#define BM_PPS_STRETCH_CFG_PPS0_EN  ((uint32)0x01U << 0U)

#define PHY_INTF_SEL_OFF  0x2080U

#define BM_PHY_INTF_SEL_CFG_RXC_DELAY_EN  ((uint32)0x01U << 5U)

#define BM_PHY_INTF_SEL_CFG_TXC_DELAY_EN  ((uint32)0x01U << 4U)

#define FM_PHY_INTF_SEL_SEL  ((uint32)0x7U << 0U)
#define FV_PHY_INTF_SEL_SEL(v) \
  (((uint32)(v) << 0U) & FM_PHY_INTF_SEL_SEL)
#define GFV_PHY_INTF_SEL_SEL(v) \
  (((uint32)(v) & FM_PHY_INTF_SEL_SEL) >> 0U)

#define CAP_COMP_OE_OFF  0x2090U

#define FM_CAP_COMP_OE_CAPTURE_COMPARE_OE  ((uint32)0xfU << 0U)
#define FV_CAP_COMP_OE_CAPTURE_COMPARE_OE(v) \
  (((uint32)(v) << 0U) & FM_CAP_COMP_OE_CAPTURE_COMPARE_OE)
#define GFV_CAP_COMP_OE_CAPTURE_COMPARE_OE(v) \
  (((uint32)(v) & FM_CAP_COMP_OE_CAPTURE_COMPARE_OE) >> 0U)

#define RMII_CLK_OE_OFF  0x2094U

#define BM_RMII_CLK_OE_CKGEN_RMII_OE  ((uint32)0x01U << 0U)

#define MAC_FLOW_CONTROL_OFF  0x20a0U

#define FM_MAC_FLOW_CONTROL_EN  ((uint32)0x7U << 0U)
#define FV_MAC_FLOW_CONTROL_EN(v) \
  (((uint32)(v) << 0U) & FM_MAC_FLOW_CONTROL_EN)
#define GFV_MAC_FLOW_CONTROL_EN(v) \
  (((uint32)(v) & FM_MAC_FLOW_CONTROL_EN) >> 0U)


#endif   /* __DWC_ETHER_QOS_WRAPPER_REG_H__ */
